The gate electrode is one of the most important functional components of MOSFET devices. Polysilicon is now typically used as the gate electrode material in the transistor gate stack. Today's transistors have poly-Si gates so highly doped as to be almost as conductive as metal. However, the solubility of dopants in poly-Si is limited to around 5×1020 atoms/cm3. The dopant solubility restricts the number of charge carriers in poly-Si. As a result, a depletion layer is formed at the polysilicon dielectric interface when the gate is biased. The depletion region increases the equivalent oxide thickness (EOT) of the gate stack at least 4–5 Å, regardless of the level to which the poly-Si is doped. As a result, it is desirable to replace poly-Si with a metallic material. In practice, metallic materials have an infinite amount of carriers (5×1022 atoms/cm3) and therefore the thickness of the depletion region is virtually zero. In other words, the EOT can be decreased 4–5 Å just by replacing the poly-Si gate with a metal gate.
One of the most important properties of the metal gate is its work function. The work function, together with the doping level of substrate, determines the threshold voltage of the MOS-transistor. The work function of a metal electrode material should be about 4.0 to 4.2 eV in NMOS field effect transistors and about 5.0–5.2 eV in PMOS field effect transistors.
Most of the research regarding metal gates/electrodes has been done in relation to the use of physical vapor deposition (PVD). PVD allows the use of a wide range of different materials. However, because of the sputter damage to the gate dielectric layer and the non-uniformity of films deposited on the substrate, it is unlikely that PVD will be used in future production of MOSFETs. Chemical vapor deposition (CVD) methods also have a number of significant drawbacks. CVD methods demand high deposition temperatures in order to achieve low impurity levels. As a result, these methods will degrade the gate dielectric layers. At lower deposition temperatures, CVD methods leave too high a concentration of impurities in the film, also degrading the gate dielectric layer.
In dual metal CMOS processing, where two different metal electrode materials are needed for the PMOS and NMOS transistors, the gate dielectric layer is exposed to etch processes after growing/depositing the first p-type gate electrode over the PMOS in order to make deposition of n-type electrode possible over the NMOS, or vice versa if the n-type gate electrode is deposited first. If the upper region of the gate dielectric layer is exposed to the etch processes used for metal gate stack patterning, the electrical properties of the MOS transistor are likely to be degraded. Thus, it would be useful to have a way to do the CMOS processing without exposing the gate dielectric layer to the etch processes.